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RISC-V adoption has increased dramatically throughout 2022, due to the architecture's simple intruction set, the ability to better pre-process NNs for acceleration and its open source nature. The advent of the RISC-V vector extension allows AI processor builders to develop on top of instructions that other companies are using and then innovate in whatever domain they want to specialize in.


Chip Design
Edge AI
ML at Scale
Novel
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Cerebras Systems builds the fastest AI accelerators in the industry. In this talk we will review how the size and scope of massive natural language processing (NLP) presents fundamental challenges to legacy compute and to traditional cloud providers. We will explore the importance of guaranteed node to node latency in large clusters, how that can’t be achieved in the cloud, and how it prevents linear and even deterministic scaling. We will examine the complexity of distributing NLP models over hundreds or thousands of GPUs and show how quickly and easily a cluster of Cerebras CS-2s is set up, and how linear scaling can be achieved over millions of compute cores with Cerebras technology. And finally, we will show how innovative customers are using clusters of Cerebras CS-2s to train large language models in order to solve both basic and applied scientific challenges, including understanding the COVID-19 replication mechanism, epigenetic language modelling for drug discovery, and in the development of clean energy. This enables researchers to test ideas that may otherwise languish for lack of resources and, ultimately, reduces the cost of curiosity.  ​

 

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

 

Stefania Avanzini

OP2B Director
World Business Council for Sustainable Development

Stefania is impact-driven and passionate about collective transformations. As Director of One Planet Business for Biodvisersity, she is working to scale the adoption of regenerative agriculture globally through the organization’s cross-sectoral membership that spans the agricultural value chain from production to distribution. Prior to her work at OP2B, Stefania worked for Danone’s investment fund for social business, and for Ashoka – the world’s largest network of social entrepreneurs.

Stefania Avanzini

OP2B Director
World Business Council for Sustainable Development

Stefania Avanzini

OP2B Director
World Business Council for Sustainable Development

Stefania is impact-driven and passionate about collective transformations. As Director of One Planet Business for Biodvisersity, she is working to scale the adoption of regenerative agriculture globally through the organization’s cross-sectoral membership that spans the agricultural value chain from production to distribution. Prior to her work at OP2B, Stefania worked for Danone’s investment fund for social business, and for Ashoka – the world’s largest network of social entrepreneurs. Stefania believes in the power of business to transform agricultural systems in a way that is beneficial for people, climate, and nature.

 

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of co

Anthony Wood

Formal Verification Lead
Graphcore

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

 

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry.

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

 

Jian Zhang

Director, Machine Learning
SambaNova Systems

Jian Zhang

Director, Machine Learning
SambaNova Systems

Jian Zhang

Director, Machine Learning
SambaNova Systems
 

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems